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OpenRAM/compiler/tests
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Hunter Nichols 04ce3d5f45 Split control logic into different tests to avoid factory errors.
2019-06-25 14:55:28 -07:00
..
golden
Added lib test which generates multiple corner models. Only does process currently.
2019-03-04 16:27:10 -08:00
00_code_format_check_test.py
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01_library_drc_test.py
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02_library_lvs_test.py
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03_contact_test.py
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_wire_test.py
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04_pand2_test.py
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04_pbitcell_test.py
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04_pbuf_test.py
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04_pdriver_test.py
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinvbuf_test.py
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04_pnand2_test.py
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04_pnand3_test.py
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04_pnor2_test.py
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04_precharge_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_test.py
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2019-05-06 06:50:15 -07:00
05_bitcell_1rw_1r_array_test.py
Merged with dev
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05_bitcell_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_test.py
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07_single_level_column_mux_array_test.py
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08_precharge_array_test.py
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08_wordline_driver_test.py
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09_sense_amp_array_test.py
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10_write_driver_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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11_dff_buf_test.py
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2019-05-06 06:50:15 -07:00
12_tri_gate_array_test.py
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2019-05-15 18:48:00 -07:00
13_delay_chain_test.py
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2019-05-06 06:50:15 -07:00
14_replica_bitline_multiport_test.py
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14_replica_bitline_test.py
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2019-05-06 06:50:15 -07:00
16_control_logic_multiport_test.py
Split control logic into different tests to avoid factory errors.
2019-06-25 14:55:28 -07:00
16_control_logic_test.py
Split control logic into different tests to avoid factory errors.
2019-06-25 14:55:28 -07:00
19_bank_select_test.py
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19_multi_bank_test.py
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19_pmulti_bank_test.py
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19_psingle_bank_test.py
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19_single_bank_1rw_1r_test.py
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19_single_bank_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_1rw_1r_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_nomux_1rw_1r_test.py
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20_sram_1bank_nomux_test.py
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20_sram_2bank_test.py
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2019-05-06 06:50:15 -07:00
21_hspice_delay_test.py
Added bitcell check to storage nodes.
2019-05-20 18:35:52 -07:00
21_hspice_setuphold_test.py
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2019-05-06 06:50:15 -07:00
21_model_delay_test.py
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21_ngspice_delay_test.py
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21_ngspice_setuphold_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_4mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_func_test.py
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22_sram_1rw_1r_1bank_nomux_func_test.py
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2019-05-06 06:50:15 -07:00
23_lib_sram_model_corners_test.py
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23_lib_sram_model_test.py
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23_lib_sram_prune_test.py
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23_lib_sram_test.py
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24_lef_sram_test.py
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25_verilog_sram_test.py
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26_pex_test.py
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30_openram_back_end_test.py
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2019-05-06 06:50:15 -07:00
30_openram_front_end_test.py
Add front and back-end test 30.
2019-04-26 15:17:19 -07:00
config_freepdk45_back_end.py
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2019-05-06 06:50:15 -07:00
config_freepdk45_front_end.py
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config_freepdk45.py
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config_scn4m_subm_back_end.py
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config_scn4m_subm_front_end.py
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config_scn4m_subm.py
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2019-05-06 06:50:15 -07:00
regress.py
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2019-05-06 06:50:15 -07:00
sram_1rw_1r_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
sram_1rw_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
testutils.py
Merged with dev
2019-05-15 18:48:00 -07:00