OpenRAM/compiler/base
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
..
contact.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
delay_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
design.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
geometry.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
graph_util.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
hierarchy_design.py Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
hierarchy_layout.py Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
hierarchy_spice.py Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py Fix space before comment 2019-06-14 08:43:41 -07:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Fix space before comment 2019-06-14 08:43:41 -07:00
utils.py Fix space before comment 2019-06-14 08:43:41 -07:00
vector.py Fix space before comment 2019-06-14 08:43:41 -07:00
verilog.py Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
wire.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_path.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00