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base
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Merge branch 'dev' into datasheet_gen
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2018-11-08 19:26:00 -08:00 |
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bitcells
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-11-08 09:59:52 -08:00 |
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characterizer
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Merge branch 'dev' into datasheet_gen
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2018-11-07 10:08:45 -08:00 |
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datasheet
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added DRC/LVS error count to datasheet
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2018-11-01 14:02:33 -07:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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gdsMill
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Allow multiple must-connect pins with the same label.
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2018-11-07 13:05:13 -08:00 |
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modules
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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pgates
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Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell.
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2018-11-02 05:59:47 -07:00 |
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router
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Allow multiple must-connect pins with the same label.
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2018-11-07 13:05:13 -08:00 |
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tests
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Enable psram 1rw 2mux layout test.
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2018-11-07 13:37:08 -08:00 |
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verify
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Remove redundant DRC run in magic.
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2018-11-05 13:30:42 -08:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Remove options from example config files
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2018-11-05 12:47:47 -08:00 |
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example_config_scn4m_subm.py
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Add magic/netgen to example config
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2018-11-07 13:54:00 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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added config file to datasheet and output files
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2018-10-31 12:29:13 -07:00 |
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openram.py
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added config file to datasheet and output files
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2018-10-31 12:29:13 -07:00 |
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options.py
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Fix openram_temp directory
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2018-10-06 08:08:01 -07:00 |
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sram.py
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added config file to datasheet and output files
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2018-10-31 12:29:13 -07:00 |
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sram_1bank.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_4bank.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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sram_base.py
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Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
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2018-10-30 22:19:26 -07:00 |
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sram_config.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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