| .. |
|
base
|
Improve comments. Simplify function interface for channel route.
|
2018-09-11 15:53:12 -07:00 |
|
characterizer
|
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
|
2018-09-10 22:06:50 -07:00 |
|
gdsMill
|
Add back LEF blockages. Remove "absolute" flags from GDS output
|
2018-09-05 09:28:43 -07:00 |
|
modules
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-11 17:33:17 -07:00 |
|
pgates
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-11 17:33:17 -07:00 |
|
router
|
Add inflate blockages and remove pins from blockages.
|
2018-09-05 11:06:17 -07:00 |
|
tests
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-11 17:33:17 -07:00 |
|
verify
|
Add none option for verify wrapper with warning messages.
|
2018-09-11 10:17:24 -07:00 |
|
Makefile
|
Add Makefile for parallel test execution.
|
2018-01-22 13:39:07 -08:00 |
|
debug.py
|
Output debug warnings and errors to stderr. Clean up regress script a bit.
|
2018-07-11 09:51:28 -07:00 |
|
example_config_freepdk45.py
|
Merge branch 'dev' into multiport_characterization
|
2018-08-29 01:27:37 -07:00 |
|
example_config_scn3me_subm.py
|
Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done.
|
2018-09-10 19:33:59 -07:00 |
|
gen_stimulus.py
|
Convert entire OpenRAM to use python3. Works with Python 3.6.
|
2018-05-14 16:15:45 -07:00 |
|
globals.py
|
Fix temp directory preservation option.
|
2018-09-05 10:02:12 -07:00 |
|
openram.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
options.py
|
Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions.
|
2018-09-09 23:25:29 -07:00 |
|
sram.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_1bank.py
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-11 17:33:17 -07:00 |
|
sram_2bank.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_4bank.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_base.py
|
Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked.
|
2018-09-09 14:14:26 -07:00 |
|
sram_config.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
bfc855b8b1