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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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2fd86958a8b542e4ebd8702efb68b4e2f5eeac81
OpenRAM/technology/scn4m_subm/tech
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Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections
2018-11-05 16:38:46 -08:00
..
__init__.py
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
LICENSE.txt
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
SCN4M_SUBM.20.tech
Update SCN4M_SUBM Magic tech file.
2018-11-05 13:31:53 -08:00
tech.py
Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
2018-10-30 22:19:26 -07:00
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