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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
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2e353639f7dc7377a1d8ac8f4d562d6027646341
OpenRAM/compiler/router
T
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Matt Guthaus 66c703d932 Simplify router code to clean it up a bit.
2019-04-22 15:30:35 -07:00
..
tests
Simplifying supply router to single grid track
2018-12-04 08:41:57 -08:00
direction.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_cell.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_path.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_utils.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
grid.py
Check membership of keys without using keys() list
2019-01-30 13:02:34 -08:00
pin_group.py
Fix instersection bug. Improve primary and secondary pin algo.
2018-12-04 16:53:04 -08:00
router_tech.py
Cleanup code. Add time breakdown for SRAM creation.
2018-12-05 09:51:17 -08:00
router.py
Check membership of keys without using keys() list
2019-01-30 13:02:34 -08:00
signal_grid.py
Convert source and target lists to sets for faster contains check.
2019-01-30 11:15:47 -08:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Simplify router code to clean it up a bit.
2019-04-22 15:30:35 -07:00
supply_router.py
Simplify router code to clean it up a bit.
2019-04-22 15:30:35 -07:00
vector3d.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
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