OpenRAM/compiler/verify
Matt Guthaus 7ead566154 Remove cell rename during DRC. Keep flatten. 2018-09-05 16:00:48 -07:00
..
__init__.py Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
assura.py Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
calibre.py Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
magic.py Remove cell rename during DRC. Keep flatten. 2018-09-05 16:00:48 -07:00