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luke
/
OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-30 01:48:33 +02:00
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2c6d3223ea6d5e8c1dcec60409f4e907ab651810
OpenRAM
/
compiler
/
sram
T
History
Bugra Onal
2c6d3223ea
Added conditional sections to template
2022-07-08 13:51:07 -07:00
..
sram_1bank.py
Multibank file generation (messy)
2022-07-08 13:51:07 -07:00
sram_base.py
add case for single spare col spare_wen_dff i/o
2022-05-26 12:18:47 -07:00
sram_config.py
Multibank file generation (messy)
2022-07-08 13:51:07 -07:00
sram_multibank_template.v
Added conditional sections to template
2022-07-08 13:51:07 -07:00
sram_multibank.py
Multibank file generation (messy)
2022-07-08 13:51:07 -07:00
sram.py
Multibank file generation (messy)
2022-07-08 13:51:07 -07:00
