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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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2bfc94fcdd6f78a97348add91369829b51b40ca3
OpenRAM/compiler/custom
T
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Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.
2021-09-07 15:56:27 -07:00
..
dff.py
Update copyright year.
2021-01-22 11:23:28 -08:00
inv_dec.py
Update copyright year.
2021-01-22 11:23:28 -08:00
nand2_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
nand3_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
nand4_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
sense_amp.py
Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.
2021-09-07 15:56:27 -07:00
tri_gate.py
Update copyright year.
2021-01-22 11:23:28 -08:00
write_driver.py
Update copyright year.
2021-01-22 11:23:28 -08:00
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