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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 08:27:11 +02:00
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27dbb95c19e99d5e826b8e3d0e517a356e52e65a
OpenRAM/technology/scn3me_subm/gds_lib
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History
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error.
2018-01-31 17:37:16 -08:00
..
cell_6t.gds
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-01-31 10:04:28 -08:00
ms_flop.gds
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.gds
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-01-31 10:04:28 -08:00
sense_amp.gds
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.gds
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.gds
Fix pin names to lower case. Fix write driver DRC errors and LVS error.
2018-01-31 17:37:16 -08:00
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