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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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2534a32e20cb4a933d9f3424a83dd55ffd062f74
OpenRAM/compiler/pgates
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Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added.
2018-12-03 12:55:48 -08:00
..
pbuf.py
Editted pbuf.py to pass regression.
2018-11-20 14:39:11 -08:00
pdriver.py
pdriver.py passes resgression tests. Size and number of inverters has been added.
2018-12-03 12:55:48 -08:00
pgate.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinv.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinvbuf.py
Add copy power pin function
2018-10-08 09:56:39 -07:00
pnand2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pnand3.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pnor2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
precharge.py
Adjust ptx positions in precharge to be under the bl rail
2018-11-09 10:26:15 -08:00
ptx.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
single_level_column_mux.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
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