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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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2468f224d99af6d06bbe75bd2fe6903480de4091
OpenRAM/compiler/verify
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Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.
2018-01-22 17:14:39 -08:00
..
__init__.py
Only check if using magic with freepdk when LVSDRC is enabled.
2018-01-17 07:38:29 -08:00
assura.py
Improve global and code structure using modules.
2017-11-16 13:52:58 -08:00
calibre.py
Initial DRC with Magic is done.
2018-01-12 14:39:42 -08:00
magic.py
SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.
2018-01-22 17:14:39 -08:00
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