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OpenRAM
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OpenRAM/compiler/modules
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Bastian Koppelmann 233ec010ff modules: Create a class that wraps all the module class names 
this removes hard coded values from the module instatiations. It also allows
users to override certain modules with their custom cells.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 		2019-12-16 16:51:38 +01:00
..
bank.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
bank_select.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
bitcell_array.py Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
control_logic.py Feedthru port edits. 2019-09-27 14:18:49 -07:00
delay_chain.py Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
dff.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
dff_array.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
dff_buf.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
dff_buf_array.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
dff_inv.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
dff_inv_array.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
dummy_array.py Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
hierarchical_decoder.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
hierarchical_predecode.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
hierarchical_predecode2x4.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
hierarchical_predecode3x8.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
module_type.py modules: Create a class that wraps all the module class names 2019-12-16 16:51:38 +01:00
multibank.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
port_address.py Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
port_data.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
precharge_array.py Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
replica_bitcell_array.py Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
replica_column.py Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
sense_amp.py Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
sense_amp_array.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
single_level_column_mux_array.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
tri_gate.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
tri_gate_array.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
wordline_driver.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
write_driver.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
write_driver_array.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
write_mask_and_array.py Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00