mirror of https://github.com/VLSIDA/OpenRAM.git
40 lines
1.0 KiB
Python
40 lines
1.0 KiB
Python
#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class bank_select_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import bank_select
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debug.info(1, "No column mux, rw control logic")
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a = bank_select.bank_select(port="rw")
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self.local_check(a)
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debug.info(1, "No column mux, w control logic")
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a = bank_select.bank_select(port="w")
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self.local_check(a)
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debug.info(1, "No column mux, r control logic")
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a = bank_select.bank_select(port="r")
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self.local_check(a)
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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