This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
Watch
1
Star
0
Fork
You've already forked OpenRAM
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
1c6d4eedd1
OpenRAM
/
technology
/
scn4m_subm
History
mrg
8021430122
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
..
gds_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
mag_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sp_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
tech
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00