mirror of https://github.com/VLSIDA/OpenRAM.git
24 lines
704 B
Python
24 lines
704 B
Python
word_size = 32
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num_words = 256
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write_size = 8
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num_rw_ports = 1
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num_r_ports = 1
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num_w_ports = 0
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tech_name = "scn4m_subm"
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nominal_corner_only = True
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route_supplies = True
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check_lvsdrc = True
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perimeter_pins = False
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#netlist_only = True
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#analytical_delay = False
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output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
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num_r_ports,
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num_w_ports,
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word_size,
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num_words,
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tech_name)
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output_path = "macro/{}".format(output_name)
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