OpenRAM/compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw...

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word_size = 32
num_words = 256
write_size = 8
num_rw_ports = 1
num_r_ports = 1
num_w_ports = 0
tech_name = "scn4m_subm"
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nominal_corner_only = True
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route_supplies = True
check_lvsdrc = True
perimeter_pins = False
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#netlist_only = True
#analytical_delay = False
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output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words,
tech_name)
output_path = "macro/{}".format(output_name)