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OpenRAM/compiler/bitcells
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Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
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bitcell_1port.py Update copyright year. 2021-01-22 11:23:28 -08:00
bitcell_2port.py Added direction information functions to 2-port bitcell modules 2021-06-21 17:19:15 -07:00
bitcell_base.py Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
col_cap_bitcell_1port.py Update copyright year. 2021-01-22 11:23:28 -08:00
col_cap_bitcell_2port.py Update copyright year. 2021-01-22 11:23:28 -08:00
dummy_bitcell_1port.py Update copyright year. 2021-01-22 11:23:28 -08:00
dummy_bitcell_2port.py Update copyright year. 2021-01-22 11:23:28 -08:00
dummy_pbitcell.py Update copyright year. 2021-01-22 11:23:28 -08:00
pbitcell.py Update copyright year. 2021-01-22 11:23:28 -08:00
replica_bitcell_1port.py Update copyright year. 2021-01-22 11:23:28 -08:00
replica_bitcell_2port.py Added direction information functions to 2-port bitcell modules 2021-06-21 17:19:15 -07:00
replica_pbitcell.py Update copyright year. 2021-01-22 11:23:28 -08:00
row_cap_bitcell_1port.py Update copyright year. 2021-01-22 11:23:28 -08:00
row_cap_bitcell_2port.py Update copyright year. 2021-01-22 11:23:28 -08:00