OpenRAM/compiler/bitcells
Jesse Cirimelli-Low 1062cbfd7f begin fixes to pbitcell, prepare multibank pex 2020-01-24 10:24:29 +00:00
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bitcell.py fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
bitcell_1rw_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
bitcell_1w_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
bitcell_base.py begin fixes to pbitcell, prepare multibank pex 2020-01-24 10:24:29 +00:00
dummy_bitcell.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell_1rw_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell_1w_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_pbitcell.py Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
pbitcell.py squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
replica_bitcell.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_bitcell_1rw_1r.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_bitcell_1w_1r.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_pbitcell.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00