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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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1a2e0046b103007cf7d40a4b757424866033cddf
OpenRAM
/
technology
/
freepdk45
/
sp_lib
T
History
mrg
ae9dbe203d
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
..
cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_1w_1r.sp
Fix error in cell width. Fix escape warning.
2019-02-24 10:48:54 -08:00
cell_6t.sp
…
dff.sp
…
dummy_cell_1rw_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_1w_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_6t.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
replica_cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_1w_1r.sp
Fix mising file
2019-02-24 11:04:56 -08:00
replica_cell_6t.sp
…
sense_amp.sp
…
tri_gate.sp
…
write_driver.sp
…
