mirror of https://github.com/VLSIDA/OpenRAM.git
289d3b3988
Comment about write driver size for write through to work, but disable write through in functional simulation. Provide warning in Verilog about write throughs. |
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| .. | ||
| contact.py | ||
| delay_data.py | ||
| design.py | ||
| geometry.py | ||
| graph_util.py | ||
| hierarchy_design.py | ||
| hierarchy_layout.py | ||
| hierarchy_spice.py | ||
| lef.py | ||
| pin_layout.py | ||
| power_data.py | ||
| route.py | ||
| utils.py | ||
| vector.py | ||
| verilog.py | ||
| wire.py | ||
| wire_path.py | ||
| wire_spice_model.py | ||