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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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17d144b5b547ba2d8ca52bb07d3bef4c1762eb18
OpenRAM/compiler/bitcells
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mrg 043018e8ba Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
..
bitcell_1rw_1r.py
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
bitcell_1w_1r.py
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
bitcell.py
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
dummy_bitcell_1rw_1r.py
Add dummy bitcell module.
2019-07-05 12:58:52 -07:00
dummy_bitcell_1w_1r.py
Add dummy bitcell module.
2019-07-05 12:58:52 -07:00
dummy_bitcell.py
Fix dummy row LVS issue
2019-06-14 15:06:04 -07:00
dummy_pbitcell.py
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
pbitcell.py
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
replica_bitcell_1rw_1r.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
replica_bitcell_1w_1r.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
replica_bitcell.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
replica_pbitcell.py
Split control logic into different tests to avoid factory errors.
2019-06-25 14:55:28 -07:00
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