Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
17716191c11b1dc2dc2da3b2b7bdcee7c45583b3
OpenRAM/compiler/verify
T
History
Matt Guthaus 33b04bbca5 Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
2018-02-05 16:02:57 -08:00
..
__init__.py
Only check if using magic with freepdk when LVSDRC is enabled.
2018-01-17 07:38:29 -08:00
assura.py
Improve global and code structure using modules.
2017-11-16 13:52:58 -08:00
calibre.py
Disable virtual connects at top level LVS with Calibre.
2018-02-05 14:52:51 -08:00
magic.py
Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
2018-02-05 16:02:57 -08:00
Powered by Gitea Version: 1.27.2 Page: 493ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API