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luke
/
OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 09:30:38 +02:00
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15089ae4f1a2d8746e737c7cf8386eb1eae28abe
OpenRAM
/
compiler
/
drc
T
History
Jesse Cirimelli-Low
3b02a8846d
sky130 rba passing :)
2022-09-12 16:07:00 -07:00
..
__init__.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
custom_cell_properties.py
sky130 rba passing :)
2022-09-12 16:07:00 -07:00
custom_layer_properties.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
design_rules.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
drc_lut.py
Update copyright year.
2021-01-22 11:23:28 -08:00
drc_value.py
Update copyright year.
2021-01-22 11:23:28 -08:00
module_type.py
Use packages for imports.
2022-07-13 15:55:57 -07:00