OpenRAM/compiler/base
Bastian Koppelmann 14e8a26246 base/pin_layout: Make rect and layer properties
only rect and layer are used to compute the hash for a pin. Having
those as properties allows us to cache the hash value and only update it
if either rect or layer are written.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2020-01-03 11:33:34 +01:00
..
contact.py Fix minwidth for multiple via bug. 2019-12-18 09:30:00 -08:00
delay_data.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
design.py Fix minwidth for multiple via bug. 2019-12-18 09:30:00 -08:00
geometry.py Remove extra cast 2019-12-05 21:33:13 -08:00
graph_util.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
hierarchy_design.py Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
hierarchy_layout.py Merge branch 'dev' into tech_migration 2019-12-19 16:23:22 -08:00
hierarchy_spice.py Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py base/pin_layout: Make rect and layer properties 2020-01-03 11:33:34 +01:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Fix space before comment 2019-06-14 08:43:41 -07:00
utils.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
vector.py Fix space before comment 2019-06-14 08:43:41 -07:00
verilog.py Feedthru port edits. 2019-09-27 14:18:49 -07:00
wire.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_path.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00