Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 08:27:11 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
0ff1d1a23dd849ab10cef4ada57f86c0ed943d86
OpenRAM/technology/freepdk45/sp_lib
T
History
Bugra Onal 3496ac8f5a Added buffer to sense_amp output (need to resize)
2023-02-21 13:23:29 -08:00
..
cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
dummy_cell_1rw.sp
fix end subckt typo
2021-02-27 18:28:07 -05:00
dummy_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.sp
Added buffer to sense_amp output (need to resize)
2023-02-21 13:23:29 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
Powered by Gitea Version: 1.27.2 Page: 157ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API