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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-06 17:35:28 +02:00
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0e96648211f11b81cc20a069b7d1c5c61f8ec63c
OpenRAM/compiler/pgates
T
History
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
..
pand2.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pbuf.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pdriver.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pgate.py
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
pinv.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pinvbuf.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pnand2.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pnand3.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pnor2.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
precharge.py
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
ptx.py
Change path to wire_path for Anaconda package conflict
2019-01-25 15:07:56 -08:00
single_level_column_mux.py
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
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