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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 03:20:39 +02:00
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0e96648211f11b81cc20a069b7d1c5c61f8ec63c
OpenRAM/compiler/bitcells
T
History
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
..
bitcell_1rw_1r.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
bitcell_1w_1r.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
bitcell.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pbitcell.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
replica_bitcell_1rw_1r.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
replica_bitcell_1w_1r.py
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_bitcell.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
replica_pbitcell.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
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