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luke
/
OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 01:24:39 +02:00
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0c3ee643ab5b64ed2cb64a8e7821757e69c8e7d5
OpenRAM
/
technology
/
freepdk45
/
tech
T
History
mrg
0c3ee643ab
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
..
__init__.py
update copyright year.
2021-01-22 11:24:53 -08:00
freepdk45.lydrc
Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
2021-11-22 11:33:27 -08:00
freepdk45.lylvs
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
freepdk45.lyp
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
freepdk45.lyt
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
scn4m_subm.lyp
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
scn4m_subm.lyt
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
tech.py
Fixed incorrect via2 spacing rule in tech file.
2021-11-22 11:33:27 -08:00
