mirror of https://github.com/VLSIDA/OpenRAM.git
214 lines
8.5 KiB
Python
214 lines
8.5 KiB
Python
import debug
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import design
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from tech import drc
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from pinv import pinv
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from contact import contact
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from vector import vector
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from globals import OPTS
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class delay_chain(design.design):
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"""
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Generate a delay chain with the given number of stages and fanout.
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This automatically adds an extra inverter with no load on the input.
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Input is a list contains the electrical effort of each stage.
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"""
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def __init__(self, fanout_list, name="delay_chain"):
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"""init function"""
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design.design.__init__(self, name)
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# FIXME: input should be logic effort value
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# and there should be functions to get
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# area efficient inverter stage list
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for f in fanout_list:
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debug.check(f>0,"Must have non-zero fanouts for each stage.")
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# number of inverters including any fanout loads.
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self.fanout_list = fanout_list
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self.num_inverters = 1 + sum(fanout_list)
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self.num_top_half = round(self.num_inverters / 2.0)
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.add_pins()
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self.create_module()
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self.route_inv()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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""" Add the pins of the delay chain"""
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self.add_pin("in")
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self.add_pin("out")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_module(self):
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""" Add the inverter logical module """
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self.create_inv_list()
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self.inv = pinv(route_output=False)
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self.add_mod(self.inv)
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# half chain length is the width of the layout
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# invs are stacked into 2 levels so input/output are close
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# extra metal is for the gnd connection U
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self.width = self.num_top_half * self.inv.width + 2*drc["metal1_to_metal1"] + 0.5*drc["minwidth_metal1"]
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self.height = 2 * self.inv.height
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self.add_inv_list()
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def create_inv_list(self):
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"""
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Generate a list of inverters. Each inverter has a stage
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number and a flag indicating if it is a dummy load. This is
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the order that they will get placed too.
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"""
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# First stage is always 0 and is not a dummy load
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self.inv_list=[[0,False]]
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for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list):
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for i in range(fanout_size-1):
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# Add the dummy loads
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self.inv_list.append([stage_num+1, True])
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# Add the gate to drive the next stage
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self.inv_list.append([stage_num+1, False])
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def add_inv_list(self):
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""" Add the inverters and connect them based on the stage list """
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dummy_load_counter = 1
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self.inv_inst_list = []
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for i in range(self.num_inverters):
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# First place the gates
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if i < self.num_top_half:
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# add top level that is upside down
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inv_offset = vector(i * self.inv.width, 2 * self.inv.height)
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inv_mirror="MX"
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else:
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# add bottom level from right to left
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inv_offset = vector((self.num_inverters - i) * self.inv.width, 0)
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inv_mirror="MY"
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cur_inv=self.add_inst(name="dinv{}".format(i),
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mod=self.inv,
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offset=inv_offset,
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mirror=inv_mirror)
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# keep track of the inverter instances so we can use them to get the pins
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self.inv_inst_list.append(cur_inv)
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# Second connect them logically
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cur_stage = self.inv_list[i][0]
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next_stage = self.inv_list[i][0]+1
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if i == 0:
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input = "in"
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else:
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input = "s{}".format(cur_stage)
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if i == self.num_inverters-1:
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output = "out"
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else:
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output = "s{}".format(next_stage)
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# if the gate is a dummy load don't connect the output
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# else reset the counter
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if self.inv_list[i][1]:
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output = output+"n{0}".format(dummy_load_counter)
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dummy_load_counter += 1
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else:
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dummy_load_counter = 1
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self.connect_inst(args=[input, output, "vdd", "gnd"])
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if i != 0:
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=cur_inv.get_pin("A").center())
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def add_route(self, pin1, pin2):
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""" This guarantees that we route from the top to bottom row correctly. """
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pin1_pos = pin1.center()
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pin2_pos = pin2.center()
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if pin1_pos.y == pin2_pos.y:
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self.add_path("metal2", [pin1_pos, pin2_pos])
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else:
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mid_point = vector(pin2_pos.x, 0.5*(pin1_pos.y+pin2_pos.y))
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# Written this way to guarantee it goes right first if we are switching rows
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self.add_path("metal2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos])
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def route_inv(self):
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""" Add metal routing for each of the fanout stages """
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start_inv = end_inv = 0
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for fanout in self.fanout_list:
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# end inv number depends on the fan out number
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end_inv = start_inv + fanout
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start_inv_inst = self.inv_inst_list[start_inv]
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start_inv_inst.get_pin("Z").center()),
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# route from output to first load
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start_inv_pin = start_inv_inst.get_pin("Z")
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load_inst = self.inv_inst_list[start_inv+1]
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load_pin = load_inst.get_pin("A")
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self.add_route(start_inv_pin, load_pin)
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next_inv = start_inv+2
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while next_inv <= end_inv:
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prev_load_inst = self.inv_inst_list[next_inv-1]
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prev_load_pin = prev_load_inst.get_pin("A")
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load_inst = self.inv_inst_list[next_inv]
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load_pin = load_inst.get_pin("A")
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self.add_route(prev_load_pin, load_pin)
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next_inv += 1
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# set the start of next one after current end
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start_inv = end_inv
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def add_layout_pins(self):
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""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
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the top end with no input/output to obstruct. """
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vdd_pin = self.inv.get_pin("vdd")
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gnd_pin = self.inv.get_pin("gnd")
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for i in range(3):
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(offset,y_dir)=self.get_gate_offset(0, self.inv.height, i)
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rail_width = self.num_top_half * self.inv.width
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if i % 2:
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=offset + vdd_pin.ll().scale(1,y_dir),
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width=rail_width,
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height=drc["minwidth_metal1"])
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else:
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=offset + gnd_pin.ll().scale(1,y_dir),
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width=rail_width,
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height=drc["minwidth_metal1"])
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# Use the right most parts of the gnd rails and add a U connector
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# We still have the two gnd pins, but it is an either-or connect
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gnd_pins = self.get_pins("gnd")
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gnd_start = gnd_pins[0].rc()
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gnd_mid1 = gnd_start + vector(2*drc["metal1_to_metal1"],0)
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gnd_end = gnd_pins[1].rc()
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gnd_mid2 = gnd_end + vector(2*drc["metal1_to_metal1"],0)
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#self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
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self.add_path("metal1", [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
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# input is A pin of first inverter
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a_pin = self.inv_inst_list[0].get_pin("A")
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self.add_layout_pin(text="in",
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layer="metal1",
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offset=a_pin.ll(),
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width=a_pin.width(),
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height=a_pin.height())
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# output is Z pin of last inverter
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z_pin = self.inv_inst_list[-1].get_pin("Z")
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self.add_layout_pin(text="out",
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layer="metal1",
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offset=z_pin.ll().scale(0,1),
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width=z_pin.lx())
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