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luke
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OpenRAM
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0adfe664296ccf8087689709c8d1291bb5bde62a
OpenRAM
/
technology
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scn3me_subm
T
History
Matt Guthaus
c3bd54696f
Merge branch 'dev' into multiport
2018-08-31 12:56:25 -07:00
..
gds_lib
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
mag_lib
Use a .magicrc in the technology directory to read magic tech files
2018-08-30 14:20:41 -07:00
models
Remove KP from SCMOS models to get rid of ngspice error.
2018-03-01 11:10:04 -08:00
sp_lib
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Preserve same order of design rules in each tech file
2018-08-29 16:12:06 -07:00
tf
Add LICENSE and README from NCSU CDK
2018-03-02 10:42:23 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00