mirror of https://github.com/VLSIDA/OpenRAM.git
55 lines
1.6 KiB
Plaintext
55 lines
1.6 KiB
Plaintext
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Use signal names from the technology file. Right now they are hard
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coded everywhere. For example: DATA, ADDR, etc.
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Cell name (ms_flop) is hard coded in characterizer, pin names are hard
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coded too. This should come from the config file which dynamically
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loads the module names.
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Autodetect ideal number of threads for hspice.
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vdd and gnd are hard coded in some places. The names should come from
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the tech file.
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Some modules use upper/lower via layer instead of min width DRC rule
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from tech file.
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Fix the size of the labels in freepdk45. They are ok in scn3me_subm though.
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Add the clock buffer internal to control logic. Simulation uses
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1-4-8-16 inverters right now. Replace simulation with simple clock
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buffer after fixing.
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Check out the multibank organization in sram.py and bank.py to see if
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it can be reduced or made more readable.
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Move/modify similar functions in hierarchical_predecode2x4 and
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hierarchical_predecode3x8 to hierarchical_predecode class
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Fix stimuli.py to be more readable.
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Change the delay measurement to be from the negative clock edge to
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remove the dependency on the clock period.
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Remove duplicate clock inverter in MS flop.
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Make lib file have delay relative to negedge for DATA. Must update
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timing code too.
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Convert characterizer into a Python package
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cal_delay_over_path functions in hierarchy_spice
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can wire as output(it only take capcitance now).
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maybe consider make rc_net a class
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dont use dictionary in analytical model make it like vector class
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add wire delay model for bank connection
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#may 15
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-explain why nand_2 fail lef
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-add bank seg for delay
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-build better sense amp
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