Use signal names from the technology file. Right now they are hard
coded everywhere. For example: DATA, ADDR, etc.

Cell name (ms_flop) is hard coded in characterizer, pin names are hard
coded too. This should come from the config file which dynamically
loads the module names.

Autodetect ideal number of threads for hspice.

vdd and gnd are hard coded in some places. The names should come from
the tech file.

Some modules use upper/lower via layer instead of min width DRC rule
from tech file.

Fix the size of the labels in freepdk45. They are ok in scn3me_subm though.

Add the clock buffer internal to control logic. Simulation uses
1-4-8-16 inverters right now.  Replace simulation with simple clock
buffer after fixing.

Check out the multibank organization in sram.py and bank.py to see if
it can be reduced or made more readable.

Move/modify similar functions in hierarchical_predecode2x4 and 
hierarchical_predecode3x8 to hierarchical_predecode class

Fix stimuli.py to be more readable.

Change the delay measurement to be from the negative clock edge to 
remove the dependency on the clock period.

Remove duplicate clock inverter in MS flop.

Make lib file have delay relative to negedge for DATA. Must update
timing code too.

Convert characterizer into a Python package

cal_delay_over_path functions in hierarchy_spice  
can wire as output(it only take capcitance now).
maybe consider make rc_net a class

dont use dictionary in analytical model make it like vector class

add wire delay model for bank connection

#may 15
-explain why nand_2 fail lef
-add bank seg for delay
-build better sense amp