mirror of https://github.com/VLSIDA/OpenRAM.git
111 lines
5.8 KiB
Markdown
111 lines
5.8 KiB
Markdown
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# OpenRAM
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[](https://www.python.org/)
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[](./LICENSE)
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[](https://pypi.org/project/openram/)
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[](https://githubtocolab.com/sfmth/openram-playground/blob/main/OpenRAM.ipynb)
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An open-source static random access memory (SRAM) compiler.
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# What is OpenRAM?
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<img align="right" width="25%" src="https://raw.githubusercontent.com/VLSIDA/OpenRAM/stable/images/SCMOS_16kb_sram.jpg">
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OpenRAM is an award winning open-source Python framework to create the layout,
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netlists, timing and power models, placement and routing models, and
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other views necessary to use SRAMs in ASIC design. OpenRAM supports
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integration in both commercial and open-source flows with both
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predictive and fabricable technologies.
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# Documentation
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Please see our [documentation][documentation] and let us know if anything needs
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updating.
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# Get Involved
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+ [Port it](./PORTING.md) to a new technology
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+ Report bugs by submitting [Github issues]
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+ Develop new features (see [how to contribute](./CONTRIBUTING.md))
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+ Submit code/fixes using a [Github pull request]
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+ Follow our [project][Github project]
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+ Read and cite our [ICCAD paper][OpenRAMpaper]
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# Further Help
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+ [Documentation][documentation]
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+ [OpenRAM Slack Workspace][Slack]
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+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
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+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
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# License
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OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE).
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# Publications
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+ [M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016.](https://escholarship.org/content/qt8x19c778/qt8x19c778_noSplash_b2b3fbbb57f1269f86d0de77865b0691.pdf)
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+ [S. Ataei, J. Stine, M. Guthaus, "A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS," International Conference on Computer Design (ICCD), 2016, pp. 499-506.](https://escholarship.org/uc/item/99f6q9c9)
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+ [E. Ebrahimi, M. Guthaus, J. Renau, "Timing Speculative SRAM," IEEE International Symposium on Circuits and Systems (ISCAS), 2017.](https://escholarship.org/content/qt7nn0j5x3/qt7nn0j5x3_noSplash_172457455e1aceba20694c3d7aa489b4.pdf)
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+ [B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization," IEEE International Symposium on Circuits and Systems (ISCAS), 2019.](https://escholarship.org/content/qt98s4c1hp/qt98s4c1hp_noSplash_753dcc3e218f60aafff98ef77fb56384.pdf)
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+ [B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://ieeexplore.ieee.org/document/8920325)
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+ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
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+ [M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software," IEEE International Electron Devices Meeting (IEDM), 2020.](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9372047)
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+ [H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
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# Contributors & Acknowledgment
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- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
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- [James Stine] from [VLSIARCH] co-founded the project.
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- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker
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If I forgot to add you, please let me know!
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[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
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[James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
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[VLSIDA]: https://vlsida.soe.ucsc.edu
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[VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
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[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
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[Github issues]: https://github.com/VLSIDA/OpenRAM/issues
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[Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls
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[Github project]: https://github.com/VLSIDA/OpenRAM
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[documentation]: docs/source/index.md
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[dev-group]: mailto:openram-dev-group@ucsc.edu
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[user-group]: mailto:openram-user-group@ucsc.edu
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[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu
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[user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu
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[Klayout]: https://www.klayout.de/
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[Magic]: http://opencircuitdesign.com/magic/
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[Netgen]: http://opencircuitdesign.com/netgen/
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[Qflow]: http://opencircuitdesign.com/qflow/history.html
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[Ngspice]: http://ngspice.sourceforge.net/
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[Xyce]: http://xyce.sandia.gov/
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[Git]: https://git-scm.com/
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[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
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[Sky130]: https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
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[Slack]: https://join.slack.com/t/openram/shared_invite/zt-onim74ue-zlttW5XI30xvdBlJGJF6JA
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