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OpenRAM/compiler/modules
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mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 		2021-04-07 16:07:56 -07:00
..
and2_dec.py Update copyright year. 2021-01-22 11:23:28 -08:00
and3_dec.py Update copyright year. 2021-01-22 11:23:28 -08:00
and4_dec.py Update copyright year. 2021-01-22 11:23:28 -08:00
bank.py Control logic route changes. 2021-03-24 14:32:10 -07:00
bank_select.py Update copyright year. 2021-01-22 11:23:28 -08:00
bitcell_array.py Reimplement trim options (except on unit tests). 2021-04-07 16:07:56 -07:00
bitcell_base_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
col_cap_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
column_mux_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
control_logic.py Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
delay_chain.py Update copyright year. 2021-01-22 11:23:28 -08:00
dff_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
dff_buf.py Update copyright year. 2021-01-22 11:23:28 -08:00
dff_buf_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
dff_inv.py Update copyright year. 2021-01-22 11:23:28 -08:00
dff_inv_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
dummy_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
global_bitcell_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
hierarchical_decoder.py Update copyright year. 2021-01-22 11:23:28 -08:00
hierarchical_predecode.py Skywater changes. 2021-03-22 15:48:14 -07:00
hierarchical_predecode2x4.py Skywater changes. 2021-03-22 15:48:14 -07:00
hierarchical_predecode3x8.py Skywater changes. 2021-03-22 15:48:14 -07:00
hierarchical_predecode4x16.py Skywater changes. 2021-03-22 15:48:14 -07:00
local_bitcell_array.py Change LWL layers 2021-04-07 16:07:56 -07:00
module_type.py Update copyright year. 2021-01-22 11:23:28 -08:00
multibank.py Update copyright year. 2021-01-22 11:23:28 -08:00
orig_bitcell_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
port_address.py Update copyright year. 2021-01-22 11:23:28 -08:00
port_data.py Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
precharge_array.py Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
replica_bitcell_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
replica_column.py Update copyright year. 2021-01-22 11:23:28 -08:00
row_cap_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
sense_amp_array.py Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
tri_gate_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
wordline_buffer_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
wordline_driver_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
write_driver_array.py Update copyright year. 2021-01-22 11:23:28 -08:00
write_mask_and_array.py Update copyright year. 2021-01-22 11:23:28 -08:00