mirror of https://github.com/VLSIDA/OpenRAM.git
63d0523228
Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules. |
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| .. | ||
| cell_6t.sue | ||
| ms_flop.sue | ||
| replica_cell_6t.sue | ||
| sense_amp.sue | ||
| tri_gate.sue | ||
| write_driver.sue | ||