Matt Guthaus 05ad4285af Cleanup pgate code. ...

Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.

2019-04-26 12:30:42 -07:00

..

contact.py

Add far left option for contact placement in pgates.

2019-04-17 13:41:35 -07:00

design.py

Improve print output for debugging layout objects.

2019-04-17 13:41:17 -07:00

geometry.py

Improve print output for debugging layout objects.

2019-04-17 13:41:17 -07:00

hierarchy_design.py

Cleanup pgate code.

2019-04-26 12:30:42 -07:00

hierarchy_layout.py

Rewrite add_contact to use layer directions.

2019-04-15 18:00:36 -07:00

hierarchy_spice.py

Cleanup pgate code.

2019-04-26 12:30:42 -07:00

lef.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

pin_layout.py

Fix instersection bug. Improve primary and secondary pin algo.

2018-12-04 16:53:04 -08:00

route.py

Rewrite add_contact to use layer directions.

2019-04-15 18:00:36 -07:00

utils.py

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

vector.py

Fix Future Warning for real

2018-10-10 15:58:16 -07:00

verilog.py

Remove tabs

2019-01-11 14:16:57 -08:00

wire_path.py

Change path to wire_path for Anaconda package conflict

2019-01-25 15:07:56 -08:00

wire.py

Rewrite add_contact to use layer directions.

2019-04-15 18:00:36 -07:00