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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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0589a35f7315fc075eaca38c0abd477703e70bf7
OpenRAM/compiler/sram
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mrg cce1305da3 Add technology parameter for library prefix during uniquification of GDS
2021-07-12 11:01:51 -07:00
..
sram_1bank.py
Add extra dnwell spacing for single port
2021-06-23 11:14:58 -07:00
sram_2bank.py
Update copyright year.
2021-01-22 11:23:28 -08:00
sram_base.py
Merge branch 'dev' into automated_analytical_model
2021-06-22 01:39:38 -07:00
sram_config.py
Reset write_size to none when it is the same as data word width
2021-07-09 12:31:35 -07:00
sram.py
Add technology parameter for library prefix during uniquification of GDS
2021-07-12 11:01:51 -07:00
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