mirror of https://github.com/VLSIDA/OpenRAM.git
101 lines
3.2 KiB
Markdown
101 lines
3.2 KiB
Markdown
### [Go Back](./index.md#table-of-contents)
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# Control Logic and Timing
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This page of the documentation explains the control logic and timing of OpenRAM.
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## Table of Contents
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1. [Read Timing](#read-timing)
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1. [Write Timing](#write-timing)
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1. [External Control Signals](#external-control-signals)
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1. [Internal Control Signals](#internal-control-signals)
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1. [Replica Bitline (RBL)](#replica-bitline-rbl)
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1. [Internal Control Signals Diagram (Read)](#internal-control-signals-diagram-read)
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1. [Internal Control Signals Diagram (Write)](#internal-control-signals-diagram-write)
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1. [Clock Distribution](#clock-distribution)
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## Read Timing
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### Read Timing Simulation
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## Write Timing
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### Write Timing Simulation
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## External Control Signals
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* Behaves as a synchronous register interface
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* Address and data captured on positive edge
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* Data is available after the negative edge (before next positive edge)
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* Clock is used for internal control generation
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* Clock cycle
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* Clock high: capture inputs + precharge + decode
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* Clock low: read/write
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* Reads and writes on multiple ports to the same address in the same cycle "feed through" but the noise margins of the bitcell must be able to handle this
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## Internal Control Signals
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* Sense Enable (`s_en`) -- Active high sense amp enable from Replica Bit Line (RB)
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* RBL input: `rbl_wl = gated_clk_bar & we_bar`
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* Delayed RBL output: `pre_s_en = DELAY(rbl_bl)`
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* Buffered enable: `s_en = BUF(pre_s_en)`
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* Write Driver Enable (`w_en`) -- Active high write driver enable
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* `w_en = we`
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* `we` is directly from control flops
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* Precharge Enable Bar (`p_en_bar`) -- Active low enable of precharge
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* `p_en_bar = !(gated_clk_bar)`
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* Active for writes as well to prevent half select destruction
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* Word line enable (`wl_en`) -- Active high word line enable
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* `wl_en = BUF(gated_clk_bar)`
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## Replica Bitline (RBL)
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<img align="right" width=300 src="../assets/images/control_logic/replica_array.png">
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* Determines when to start sensing by replicating a bitcell array column
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* Replica Bitline Column (RBC) matches transition of column
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* `rbl_bl = RBC(rbl_wl)`
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* Delay Line delays the input signal to match word line driver
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* `pre_s_en = DELAY(rbl_bl)`
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* Buffer drives `s_en` signal to sense amps
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## Internal Control Signals Diagram (Read)
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## Internal Control Signals Diagram (Write)
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## Clock Distribution
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* External clock (`clk`)
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* Buffered clock (`clk_buf`) drives all DFFs in the design
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* `clk_buf = BUF(clk)`
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* Buffered clock bar (`clk_bar`) used in control logic
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* `clk_bar = INV(clk_buf)`
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* Gated Clocks (`gated_clk` and `gated_clk_bar`) used in control logic
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* This is LOW when disabled
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* `gated_clk_bar = cs && clk_bar`
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* This is LOW when disabled
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* `gated_clk = cs && clk_buf`
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