mirror of https://github.com/VLSIDA/OpenRAM.git
66 lines
2.2 KiB
Python
66 lines
2.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from sram_factory import factory
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from globals import OPTS
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class dummy_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, cols, rows, column_offset=0, mirror=0, name=""):
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super().__init__(cols, rows, name, column_offset)
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
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self.add_mod(self.dummy_cell)
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(col, row))
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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bitcell_wl_cin = self.cell.get_wl_cin()
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total_cin = bitcell_wl_cin * self.column_size
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return total_cin
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