mirror of https://github.com/VLSIDA/OpenRAM.git
DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again. |
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| .. | ||
| cell_6t.mag | ||
| ms_flop.mag | ||
| replica_cell_6t.mag | ||
| sense_amp.mag | ||
| tri_gate.mag | ||
| write_driver.mag | ||