luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
01cbc71a2a68f9d41fe87d267e254c99e7711ab9
OpenRAM/compiler/tests
T
History
Matt Guthaus 0e0516c4a6 Fix delay test unit test results.
2018-07-26 16:45:09 -07:00
..
golden
Initial merge of incomplete multi-port clean with new supply routing.
2018-05-11 08:18:04 -07:00
00_code_format_check_test.py
Change permissions of tests to be executable so you don't have to type python each time.
2018-06-29 11:36:30 -07:00
01_library_drc_test.py
Remove extra conversion to list
2018-07-11 12:07:37 -07:00
02_library_lvs_test.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
03_contact_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_path_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_1finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_1finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_3finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_3finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_4finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_4finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_wire_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pbitcell_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_1x_beta_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_1x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_2x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_10x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinvbuf_test.py
Fix pinvbuf test to use new interface with only driver size.
2018-07-26 14:20:00 -07:00
04_pnand2_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pnand3_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pnor2_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_precharge_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_single_level_column_mux_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
05_bitcell_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
05_pbitcell_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_decoder_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_predecode2x4_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_predecode3x8_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
07_single_level_column_mux_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
08_precharge_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
08_wordline_driver_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
09_sense_amp_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
10_write_driver_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_buf_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_buf_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_inv_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_inv_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_ms_flop_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
12_tri_gate_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
13_delay_chain_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
14_replica_bitline_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
16_control_logic_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
19_bank_select_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
19_multi_bank_test.py
Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
2018-07-17 15:13:00 -07:00
19_single_bank_test.py
Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
2018-07-17 15:13:00 -07:00
20_sram_1bank_test.py
Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
2018-07-17 15:13:00 -07:00
20_sram_2bank_test.py
Fix syntax error in unit test
2018-07-17 15:14:22 -07:00
20_sram_4bank_test.py
Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
2018-07-17 15:13:00 -07:00
21_hspice_delay_test.py
Update format of delay test output during an error to directly
2018-07-26 16:05:24 -07:00
21_hspice_setuphold_test.py
Update format of delay test output during an error to directly
2018-07-26 16:05:24 -07:00
21_ngspice_delay_test.py
Fix delay test unit test results.
2018-07-26 16:45:09 -07:00
21_ngspice_setuphold_test.py
Update format of delay test output during an error to directly
2018-07-26 16:05:24 -07:00
22_pex_test.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
22_sram_func_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
23_lib_sram_model_test.py
Pass the sram design to lib instead of the sram wrapper
2018-07-18 11:51:42 -07:00
23_lib_sram_prune_test.py
Pass the sram design to lib instead of the sram wrapper
2018-07-18 11:51:42 -07:00
23_lib_sram_test.py
Pass the sram design to lib instead of the sram wrapper
2018-07-18 11:51:42 -07:00
24_lef_sram_test.py
Disable LEF test until supplies fixed.
2018-07-11 14:18:53 -07:00
25_verilog_sram_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
30_openram_test.py
Close output log in test 30 to avoid warning
2018-07-26 14:01:40 -07:00
config_20_freepdk45.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
config_20_scn3me_subm.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
regress.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
testutils.py
Fix delay test unit test results.
2018-07-26 16:45:09 -07:00