Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections		2018-11-05 16:38:46 -08:00
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cell_1rw_1r.gds	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
cell_6t.gds	changing case of pins in handmade cell_6t for freepdk45	2018-05-22 14:19:26 -07:00
dff.gds	Add dff_buf and dff_array modules.	2018-03-23 08:11:51 -07:00
replica_cell_1rw_1r.gds	Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.	2018-11-01 12:29:49 -07:00
replica_cell_6t.gds	Change freepdk45 rbl cell too.	2018-11-05 11:02:11 -08:00
sense_amp.gds	Flip sense amp y axis	2018-04-23 10:19:26 -07:00
tri_gate.gds	Move sense amp to tri gate routing to M3... not ideal.	2018-04-23 09:14:18 -07:00
write_driver.gds	Fix write driver gnd pin layer text	2018-04-11 09:34:13 -07:00