mirror of https://github.com/VLSIDA/OpenRAM.git
41 lines
2.1 KiB
Markdown
41 lines
2.1 KiB
Markdown
### [Go Back](./index.md#table-of-contents)
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# Bitcells
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This page of the documentation explains the bitcells supported by OpenRAM.
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## Table of Contents
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1. [Multiport Bitcells](#multiport-bitcells)
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1. [Relative Bitcell Sizes](#relative-bitcell-sizes-035um-scmos)
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1. [Thin SRAM Bitcells](#thin-sram-bitcells-130nm)
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## Multiport Bitcells
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* Based on 6T SRAM cell
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* Standard read-write
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* Isolated read-only ports
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* Write-only port (not sized for reads)
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* Can accommodate foundry bitcells
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## Relative Bitcell Sizes (0.35um SCMOS)
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| <img height="184" src="../assets/images/bitcells/6t.png"> | <img height="278" src="../assets/images/bitcells/10t.png"> | <img height="424" src="../assets/images/bitcells/dff.png"> |
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| :-----------------------------------------------: | :------------------------------------------------: | :--------------------------------------------------: |
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| Standard 6T (1rw) 6.8um x 9.2um | Isolated Read 10T (1rw, 1r) 10.9um x 13.9um | DFF 21.9um x 21.2um (from OSU standard cell library) |
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## Thin SRAM Bitcells (130nm)
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| <img height="158" src="../assets/images/bitcells/thin_single.png"> | <img height="158" src="../assets/images/bitcells/thin_dual.png"> | <img height="158" src="../assets/images/bitcells/thin_single_straps.png"> | <img height="197" src="../assets/images/bitcells/thin_dual_straps.png"> |
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| :--------------------------------------------------------: | :------------------------------------------------------: | :-----------------------------------------------------------------: | :-------------------------------------------------------------: |
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| Single Port 1.2um x 1.58um | Dual Port 2.40um x 1.58um | Single Port (w/ straps & taps) 2.49um x 1.58um | Dual Port (w/ straps & taps) 3.12um x 1.97um |
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| <img height="707" src="../assets/images/bitcells/dff_reference.png"> |
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| :----------------------------------------------------------: |
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| DFF (for reference) 5.83um x 7.07 um |
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