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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-28 17:14:54 +02:00
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OpenRAM
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technology
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scn4m_subm
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History
Jesse Cirimelli-Low
e7829cf641
allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
..
gds_lib
Sense amp fixes
2023-04-19 12:42:02 -07:00
mag_lib
Sense amp fixes
2023-04-19 12:42:02 -07:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sim_data
Added more data for regression modules.
2021-06-21 17:21:00 -07:00
sp_lib
Added buff to sense_amp in scmos
2023-04-12 11:49:32 -07:00
tech
allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
Fix path to tech and spice models.
2023-02-17 17:32:30 -08:00
