Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-28 17:14:54 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
dev
OpenRAM/technology/freepdk45
T
History
Jesse Cirimelli-Low e7829cf641 allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
..
gds_lib
Moved freepdk sense amp dout pin away from gnd pin
2023-05-23 15:08:06 -07:00
models
Include and use FreePDK45 models with license.
2023-02-17 15:37:53 -08:00
sim_data
Added more data for regression modules.
2021-06-21 17:21:00 -07:00
sp_lib
Sense amp fixes
2023-04-19 12:42:02 -07:00
tech
allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
tf
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
__init__.py
Fix path to tech and spice models.
2023-02-17 17:32:30 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
Powered by Gitea Version: 1.27.2 Page: 263ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API