OpenRAM

__init__.py

Merge branch 'singleport_refactor' into array_gen

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and2_dec.py

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and3_dec.py

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and4_dec.py

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bank.py

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bitcell_1port.py

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bitcell_2port.py

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bitcell_array.py

sky130 cypress dp working with offset relative to crba

2026-04-27 17:24:13 -07:00

bitcell_base_array.py

add fix for cypress sp wls

2026-04-28 17:19:54 -07:00

bitcell_base.py

squash commits

2026-04-22 01:33:47 -07:00

capped_replica_bitcell_array.py

make contacts perpendicular to power rails to avoid drc violations

2026-05-07 15:03:53 -07:00

col_cap_array.py

sky130 cypress dp working with offset relative to crba

2026-04-27 17:24:13 -07:00

col_cap_bitcell_1port.py

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col_cap_bitcell_2port.py

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column_decoder.py

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column_mux_array.py

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column_mux.py

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control_logic_base.py

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control_logic_delay.py

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control_logic.py

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delay_chain.py

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dff_array.py

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dff_buf_array.py

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dff_buf.py

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dff_inv_array.py

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dff_inv.py

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dff.py

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dummy_array.py

parameterize how power ring is connected to crba

2026-05-06 09:50:56 -07:00

dummy_bitcell_1port.py

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dummy_bitcell_2port.py

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dummy_pbitcell.py

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global_bitcell_array.py

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hierarchical_decoder.py

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hierarchical_predecode2x4.py

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hierarchical_predecode3x8.py

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hierarchical_predecode4x16.py

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hierarchical_predecode.py

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internal_base.py

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inv_dec.py

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local_bitcell_array.py

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multi_delay_chain.py

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multibank.py

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nand2_dec.py

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nand3_dec.py

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nand4_dec.py

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pand2.py

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pand3.py

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pand4.py

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pattern.py

squash commits

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pbitcell.py

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pbuf_dec.py

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pbuf.py

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pdriver.py

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pgate.py

Merge branch 'singleport_refactor' into array_gen

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pinv_dec.py

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pinv.py

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pinvbuf.py

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pnand2.py

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pnand3.py

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pnand4.py

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pnor2.py

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port_address.py

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port_data.py

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precharge_array.py

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precharge.py

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ptristate_inv.py

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ptx.py

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pwrite_driver.py

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replica_bitcell_1port.py

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replica_bitcell_2port.py

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replica_bitcell_array.py

sky130 cypress dp working with offset relative to crba

2026-04-27 17:24:13 -07:00

replica_column.py

change power ring spacing from magic numbers to drc based

2026-05-07 14:18:58 -07:00

replica_pbitcell.py

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rom_address_control_array.py

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rom_address_control_buf.py

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rom_bank.py

Add gf180mcu ROM example

2024-02-03 11:31:58 +01:00

rom_base_array.py

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rom_base_cell.py

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rom_column_mux_array.py

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rom_column_mux.py

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rom_control_logic.py

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rom_decoder.py

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rom_poly_tap.py

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rom_precharge_array.py

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rom_precharge_cell.py

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rom_wordline_driver_array.py

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row_cap_array.py

add fix for cypress sp wls

2026-04-28 17:19:54 -07:00

row_cap_bitcell_1port.py

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row_cap_bitcell_2port.py

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sense_amp_array.py

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sense_amp.py

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sram_1bank.py

Merge branch 'singleport_refactor' into array_gen

2025-02-24 23:26:28 -08:00

sram_multibank_template.v

Shrunk address register in multibank verilog

2022-07-28 15:03:41 -07:00

sram_multibank.py

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template.py

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tri_gate_array.py

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tri_gate.py

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wordline_buffer_array.py

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wordline_driver_array.py

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wordline_driver.py

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write_driver_array.py

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write_driver.py

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write_mask_and_array.py

Merge branch 'singleport_refactor' into array_gen

2025-02-24 23:26:28 -08:00