8 Commits

Author	SHA1	Message	Date
Matt Guthaus	ffcf58100e	Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.	2018-02-02 15:17:21 -08:00
Matt Guthaus	27dbb95c19	Fix name of column mux.	2018-02-02 14:26:39 -08:00
Matt Guthaus	acf3fe8376	Add well around column muxes.	2018-01-31 14:31:50 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	d17711c394	Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way.	2017-08-24 16:22:14 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00