11 Commits

Author	SHA1	Message	Date
Matt Guthaus	ffcf58100e	Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.	2018-02-02 15:17:21 -08:00
Matt Guthaus	27dbb95c19	Fix name of column mux.	2018-02-02 14:26:39 -08:00
Matt Guthaus	313e06d2af	Fix pwell contact in column mux to have layers for Magic.	2018-01-29 15:53:22 -08:00
Matt Guthaus	490a70dee9	Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.	2018-01-19 16:38:19 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	cffcd46f6d	Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.	2017-04-26 14:33:03 -07:00
Bin wu	072a65a511	add rotate_scale function in vector and use it everywhere	2016-11-11 14:33:19 -08:00
Matt Guthaus	e1c3d77a5d	Removed import cell since cell is removed from simplified txt file	2016-11-09 12:20:52 -08:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00