3 Commits

Author	SHA1	Message	Date
Michael Timothy Grimes	4d3f01ff2f	The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS ... There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell	2018-02-28 11:14:53 -08:00
Michael Timothy Grimes	4ea2a70a1b	removing unnecessary unit test for pbitcell	2018-02-19 10:58:08 -08:00
Michael Timothy Grimes	b90f5c9a59	pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd ... current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports	2018-02-08 14:21:15 -08:00